Nick -> Projects -> 8-Bit CMOS Adder

ECE 382 Final Project

Gate Level Layout of an 8-Bit Adder

By Nick Shin ECE 382 12/20/96

NOTE: All the layout and chart diagrams are linked to the image file so that this page can be loaded in quicker.


DESIGN: The adder design used in this project consists of two XOR2 gates and three NAND2 gates. The symbolic diagram of the full adder is as follows:
Full Adder Diagram

Figure 1: Full Adder in symbolic form


This schematic is based on the full adder derived from the ECE290 text book. Looking deeper into the design -- on the transistor level -- its layout is pretty much straight forward.

The XOR2 gate design is based on a 8 transistor design that was derived from the ECE325 manual. It is known as the double rail transistor. The XOR2 layout is on Figure 2 and the timing diagram is on Figure 3. It can be seen on the timing diagrams, the XOR2 design works as it is suppose to.
(XOR2 Spice File printout)

Figure 2: XOR2 Gate Layout


The NAND2 gate design was straight from the ECE382 text book. This device also works as it is suppose to. The layout of the NAND2 device is on Figure 4 and the timing diagram on Figure 5.
(NAND2 Spice File printout)

Figure 4: NAND2 Gate Layout


Before diving into the full 8-bit adder, the task was divided up into smaller managable pieces. A half-adder was constructed to see if the device would yield proper results.

This half-adder layout consisted of one XOR2 gate and one NAND2 gate (Figure 6). The timing diagram for this device has yield favorable results (timing diagram -- Figure 7). So a full-adder is the next logical step. But before continuing, the layout was redone to compressed the footprint size requirements. It was retested (simulated) and passed.
(Half Adder Spice File printout)

Figure 6: Half Adder Gate Layout


The full-adder was putting all the pieces together. The layout is on Figure 8 where it looks like just putting two half-adders together, but an additional NAND2 gate was placed at the end of the circuit to complete the carry solution. The device was tested (twice - once without CIN and once with CIN) and passed with flying colors -- Figure 9 and Figure 10.
(Full Adder Spice File with out CIN printout)
(Full Adder Spice File with CIN printout)

Figure 8: Full Adder Gate Layout


Now, technically the 8-bit adder device should work by just coping and pasting the full-adder seven more times. With a few minor layout adjustments this was completed and tested with the required test cases. The full layout of the 8-bit adder is on Figure 11 and the test cases follows (Figure 12a, Figure 12b, Figure 13a and Figure 13b). The tested carried out were to see the complete switching states of the SUM and CARRY bits. These information will be used later for power consumption analysis.
(8-Bit Adder Spice File running @ 5 V printout)
(8-Bit Adder Spice File running @ 3.3 V printout)

Figure 11: 8-Bit Adder Gate Layout


STRATEGY Since I was on my own on this project, I decided that the parallel adder was the best design for completing this assignment. The only thing that I needed was a well plan of action in developing this adder to produce the results quickly and correct. I choose the simple design of two XOR2 and three NAND2 gates because it seemed to be the tried and true tested design. I have tried implementing the designs shown in the back of the book (PG producers, Manchester devices and the tapered latch circuit) but they did not operate properly in Spice. And since I was the only person working on this and have already spent too much time trying to figure out why one design did not worked better than another, I just went right back to the basics. And what do you know! It works.


CRITICAL PATH The critical path in my design is the very last sumout bit (SUM7 or if you really want to get technical it is the carryout bit of the last stage -- COUT7 -- but that isn't used for anything useful in this project).

This was outlined on the 8-bit adder diagram (Figure 11). The solution of the very first carryout has to traverse through all of the CIN lines (see Figure 1) over and over again until it hits the most significant bit.

Once it makes it to the most significant bit spot, the time it takes for the adder to solve for a problem can now be measured. This is determined by seeing when SUM7 stabilizes (to within 10% of the final solution). And from Figure 12b, SUM7 reaches the final solution at about 10ns when the voltage (Vdd) is 5 Vdc. But at 3.3 Vdc, SUM7 stabilizes at just under 20ns (Figure 13b).


POWER Using the power meter design that SPICE can plot out, power dissipation can now be determined. (And I can't seem to get this part of the project to work properly in SPICE.)


TABLE of RESULTS
POWER SPEED AREA POWER DISSIPATION
5 Vdc =10 ns 288120mm2 N/A
3.3 Vdc < 20 ns 288120mm2 N/A


CONCLUSION This was an interesting project. I have learned how integrated circuit chips are designed from the ground up and giving me (the user/designer) the experience of seeing how tough it can be designing them.

This project also showed that there are many different ways to design a solution. I wished there were more people in my group. But the one I was originally teamed up with did not do anything until it was too late.

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